Implementation of Amplitude Modulation on
Software Defined Radio
K.Satyanarayana 1 , Madhekar Suneel 2 , Ravi Ranjan 2
Indian Institute of Technology-Madras, Chennai-600036, email@example.com
2 PGAD, Defence Research and Development Organisation, Hyderabad-500058, firstname.lastname@example.org
Abstract — An amplitude modulation transceiver design is
presented, using a software defined radio platform. Model
based design is used to implement the various transmitter
and receiver blocks. The wireless communication of audio
signals is demonstrated.
Index Terms — Software radio, wireless communication, am-
plitude modulation, demodulation.
This papers presents a design of an amplitude modu-
lation (AM) transceiver. The modulation scheme used is
double sideband modulation. The demodulation is carried
out using an envelope detector. The entire implementation
is carried out on a software defined radio (SDR) platform.
The SDR platform used is the Lyrtech Small Form Factor
(SFF) platform. Model based design is used as the de-
sign method. This method relies on Matlab®, Simulink®,
Texas Instruments® Code Composer Studio® and Xilinx®
II. Amplitude Modulation
Amplitude modulation is defined as a process in which
the amplitude of the carrier wave A c cos(27rf c t) is varied
about a mean value, linearly with the baseband message
signal m(t), where, A c is the carrier amplitude, f c is the
frequency of the carrier signal and t is time. The amplitude
modulated signal is given by
s(t) =Ac[l + k a m (£)] cos (2nf c t) ,
where, k a is the amplitude sensitivity of the modulation
scheme. In frequency domain, this can be expressed as
S(f) = -y[*(/-/c) + *(/ + /c)] +
^[M(/-/ c ) + M(/ + / c )].
III. Software Defined Radio
SDR is a wireless technology created to improve interop-
erability between different wireless networks, field radios,
and devices. With this technology, we can create multi-
mode, multi-band, and multi-functional wireless devices
and network equipment that can be dynamically recon-
figured, enhanced, and upgraded through software updates
® All trademarks are property of their respective owners
and hardware reconfiguration. An SDR consists of three
main modules Fig 2, namely, data conversion module,
digital signal processing module and RF section module
. A picture of the SDR platform used to carry out this
work is shown in Fig 1.
' . B
Fig. 1 : SDR platform with mobile phone as audio source
A. Digital signal processing module
The digital signal processing (DSP) module contains a
six core TMS320DM6446DSP processor, and a Xilinx®
Virtex-4® FPGA. The processor is clocked at 594 MHz.
The processor and the FPGA form the main signal process-
ing devices of the radio platform. The DSP module also
contains an audio codec.
B. Data conversion module
This module contains two analog input channels with
14 bit, 125 MSPS analog to digital converters (ADC).
The ADC used is a Texas Instruments® ADS5500 .
This module also contains two analog outputs driven by a
dual channel 16-bit, 500-MSPS digital to analog converter
(DAC). The DAC used is a Texas Instruments® DAC5687
. Besides, there are two external clock inputs and on-
board clock synthesizer.
C. RF module
This module has a radio frequency transceiver with
frequency range 1.6 GHz to 2.2 GHz. The intermediate
frequency bandwidth is selectable between 5 MHz and
20 MHz. The maximum gain provided is 22 dB. The RF certain other platform- specific configuration blocks. The
section sensitivity is -110 dBm at a signal to noise ratio of FPGA model receives the samples from the DSP, the FPGA
10 dB and a signal bandwidth of 1 kHz. model is shown in Fig 4.
Data conversion module
Digital signal processing module
90 degree phaser
Fig. 4: FPGA model showing AM modulation
The received signal is first upsampled to 125 MSPS, the
upsampling to 125 MSPS in Fig 4 is shown in figure 5.
Fig. 2: Schematic of the modules
IV. Description of AM transmitter
The description of the AM transmitter is in two parts,
namely, the DSP model and the FPGA model. The DSP
model is implemented in the DSP, and acts as an interface
between the audio signal source, and the FPGA. With
the on-board audio codec as the signal source, a DSP
model is shown in Fig 3. The audio codec is configured to
Da ta type conv ersion
Audio code I/O
RF Module Control
Fig. 3: DSP transmitter model
generate output samples at 24.414 kHz. A Video Processing
Subsystem (VPSS) bus is used to communicate the received
samples to the FPGA. The VPSS bus provides 32-bit
interface between DSP to FPGA and FPGA to DSP. The
VPSS bus is provided with the Video Processing Front
End (VPFE) directs the signal to DSP and the Video
Processing Back End (VPBE) directs the signal to the
FPGA. The VPFE is clocked at 75 MHz and the VPBE
is clocked at 37.5 MHz. The DSP model also contains
blocks to configure the RF section, the audio codec and
the ADACMaster-III data conversion module, apart from
( 1 ) — ► In1 Out1
x10 Interpolator X 8 Interpolator x 8 Interpolator! x8 Interpolator
Fig. 5: Upsampling to 125 MSPS
The upsampling by 8 block (x8 interpolator) is imple-
mented as shown in Fig 6. The other upsampling blocks
in Fig 5 are implemented in a similar manner.
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Convert Slicel Reinterpret
Fig. 6: Upsampling by a factor 8
The upsampled signal is amplitude modulated using a
1 MHz carrier waveform. The carrier is generated using a
direct digital synthesis (DDS) block as shown in Fig 7.
The modulated signal is given to the DAC, for upcon-
version to the Intermediate Frequency (IF). In the DAC,
single side band modulation mode is enabled. This IF
signal is then given to the RF module for upconversion
and transmission. The transmission frequency used in the
present work is 1700 MHz.
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cast — Wa:b] ■
Convert Slicel Reinterpret
Fig. 7: Amplitude modulation
Fig. 10: Downsampling by a factor 8
V. Description of AM receiver
The transmitted signal propagates over the air, and is
received by the receive antenna of the RF module. The
RF module down-converts it to the IF of 30 MHz. This IF
signal is fed to one of the ADC inputs of the ADACMaster-
III data conversion module. The digitized signal is provided
as input to the signal processing module. In the signal
processing module, the description is again in two parts,
namely the DSP model and the FPGA model. FPGA model
is shown in figure 8.
& D ownsamplin c
Fig. 11: Envelope Detector
Fig. 8: FPGA model showing AM demodulation
In the FPGA model the signal is first downconverted by
30 MHz , as shown in Fig 9 and downsampled by factor
8 as shown in Fig 10. This down-sampled signal is fed
30 Mhz DDS
— J z" Jnterp ► b
. Delay for Retiming Reinterpretl
Fig. 9: Downconversion
to the input of an envelope detector block, shown in Fig
11. The envelope detector demodulates the AM signal. The
demodulated signal is further down-sampled to 24.414 kHz
by downsampling blocks, as shown in Fig 12.
The down-sampling blocks in Fig 12 are implemented
in a similar manner as in Fig 10.
This signal is communicated from the FPGA,
another VPSS bus to the DSP .
In the DSP model this signal is fed to the DC offset
block. This block adjusts the DC of the signal. This
adjusted signal is fed to the audio codec with samples at
24.414 kHz, as shown in Fig 13.
Decimatorl by 8
Decimator2 by £
Decimator3 by 10
Fig. 12: Downsampling to 24.414 kHz
*!J!J|.' CMD File Generator Set bitstream Lyrlech priority manager Audio codec C
Data Type Conversion
Audio Codec I/O
0.8 1 1.2
Fig. 13: DSP receiver model
Fig. 16: Received signal in time domain
The results are taken from Simulink® so there is a
time delay between the transmitted baseband signal and the
received signal. There is a DC component in the received
spectrum as an effect of envelope detection.
Fig 14 and Fig 15 are baseband signals (audio) from the
Tx wave and Tx spectrum in the Fig 3
Fig. 14: Signal from audio codec in time domain
50 100 150 200 250 300 350 400 450 500
le 8567 Frequency(mHz)
Fig. 17: Received signal in frequency domain
 Rodger H. Hosking. Software Defined Radio Handbook, Pentek Inc,
New Jersey, 2011.
 Jeffrey H. Reed. Software Radio: A Modern Approach to Radio
Engineering, Pearson Education, New Jersey, 2002.
 Simon Haykin. Communication Systems, Wiley, New York, 3rd ed,
 Texas Instruments® ADS5500 datasheet available at http://www.ti.
 Texas Instruments® DAC5687 datasheet available at http://www.ti.
200 250 300 350 400
Fig. 15: Signal from audio codec in frequency domain
Fig 16 and Fig 17 are baseband signals (audio) from
the Rx wave and Rx spectrum in the Fig 13. The received
signal was played back on a speaker and reproduced well.